1. Field of the Invention
The present invention relates to variable delay lines and more particularly to a variable-delay, digital tapped delay line.
2. State of the Art
In digital frequency synthesis, a square-wave clock signal of a given reference frequency may be used to generate digital signals of a wide range of frequencies by subdividing the clock period into a number of equal subdivisions, producing digital signals corresponding to each subdivision, and selecting for output the digital signal having a time of occurrence most nearly coincident with the time of occurrence of signal transitions in the desired output signal. Such a technique may be described generally as vernier interpolation, a particular instant of time between the beginning and end of a reference clock period being interpolated using a time scale (vernier) calibrated to indicate fractional parts of a clock period.
In effect, vernier interpolation provides time filtering information as a fraction of the applied clock period. Commands to the time filter therefore represent relative time, and not absolute time. This difference may be explained as follows. Assume that the interval between a time t1 and a time t2 represents a time interval to be spanned using smaller equal time intervals. In absolute time division, the smaller intervals are each of a fixed duration .DELTA.t.sub.f. When a number of the smaller intervals are added together in an attempt to match the large interval, an interval match error will usually occur between the time t.sub.2 and the end of the last smaller time interval. In relative time division, the smaller time intervals are each of a variable duration .DELTA.t.sub.i set equal to (1N) (t.sub.2 -t.sub.1) such that N of the smaller intervals added together exactly equals the interval between t.sub.1 and t.sub.2.
According to the foregoing explanation, for vernier interpolation, a delay structure must be built that is calibrated and operates in relative time. Conventional delay lines that are implemented to achieve a particular time resolution are therefore not applicable to vernier interpolation.
Furthermore, to be used with vernier interpolation, a line must be designed to provide equal delay intervals between taps. As the overall delay of the line is varied, each tap interval must align to an exact fraction of the total delay. The output signal quality is dependent on the uniformity of the tap intervals and on the total number of taps.
To achieve the desired uniformity of tap intervals, the delay circuit should be fully integrable and sufficiently small to fit on a single integrated circuit chip. On any specific IC die, spatial gradients of transistor parameters are generally small. The closer the transistors are physically, the more likely they are to exhibit identical characteristics.
The foregoing criteria are satisfied by a delay line structure disclosed in U.S. application Ser. No. 07/917,322 filed Jul. 23, 1992 entitled "Variable Delay Digital Tapped Delay Line", incorporated herein by reference. Using the foregoing delay line structure, time resolution in the 50 to 90 picosecond range may be obtained. It would be desirable to be able to achieve a finer time resolution in the range of one picosecond or a few picoseconds. Such fine resolution may be achieved using the binary-controlled digital tapped delay line of the present invention in cooperation with the aforementioned delay line structure. In effect, the aforementioned delay line structure is used as a coarse delay line to achieve relatively coarse subdivision of a time interval to be spanned, and the delay line structure of the present invention is used as a fine delay line to subdivide much more finely a particular subdivision of interest of the coarse delay line.